The present invention relates to a driving circuit of a flat display device and a flat display device, and it is applicable, for example, to a display device using organic EL (Electro Luminescence) elements. The present invention makes it possible to correct light emission characteristics variously, effectively avoid significant degradation in image quality due to noise, and further simplify an adjustment operation by generating original reference voltages by selecting a plurality of candidate voltages formed by voltage divider circuits according to original reference voltage setting data, generating reference voltages for digital-to-analog conversion from the original reference voltages, generating the reference voltages at both ends by dividing a reference voltage generating voltage by the voltage divider circuit, and generating the other original reference voltages with voltage divider circuits connected in series with each other and the reference voltages at both ends used as a reference.
Conventionally, a liquid crystal display device as one type of flat display device changes gamma characteristics by the setting of reference voltages used for digital-to-analog conversion processing, as disclosed in Japanese Patent Laid-Open No. Hei 10-333648, for example.
Specifically, as shown in FIG. 8, the liquid crystal display device 1 has pixels (P) 3R, 3G, and 3B each formed by a liquid crystal cell, a switching device for the liquid crystal cell, a storage capacitor, and a display unit 2 formed by arranging the pixels 3R, 3G, and 3B in the form of a matrix. Each of the pixels 3R, 3G, and 3B in the display unit 2 of the liquid crystal display device 1 is connected to a horizontal driving circuit 4 and a vertical driving circuit 5 via a signal line (column line) SIG and a gate line (row line) G. The vertical driving circuit 5 sequentially selects the pixels 3R, 3G, and 3B, and gradation levels of the pixels 3R, 3G, and 3B are set by driving signals from the horizontal driving circuit 4, whereby a desired image is displayed. The pixels 3R, 3G, and 3B provided with red, green, and blue color filters, respectively, are arranged sequentially and cyclically so that a color image can be displayed.
For this, the liquid crystal display device 1 inputs red, green, and blue image data DR, DG, and DB to be used for display in parallel from a device main unit 6 to a controller 7. The vertical driving circuit 5 drives the gate lines G of the display unit 2 by a timing signal synchronous with the image data DR, DG, and DB. Image data D1 for one system is generated by time-division-multiplexing the image data DR, DG, and DB so as to correspond to driving of the signal lines SIG by the horizontal driving circuit 4, and the signal lines SIG are driven by the horizontal driving circuit 4 on the basis of the image data D1.
FIG. 9 is a block diagram showing in detail the horizontal driving circuit 4 and the controller 7 in conjunction with a related configuration. The controller 7 sequentially stores the image data DR, DG, and DB output from the device main unit 6 in a memory 10 and outputs the image data by control of a memory control circuit 9. The controller 7 thereby time-division-multiplexes the image data DR, DG, and DB such that image data for the same color is contiguous in a line unit with a horizontal scanning period as a unit so as to correspond to the driving of the signal lines SIG by the horizontal driving circuit 4, and then it outputs the time-division-multiplexed image data D1 for one system. Specifically, as to the pixels 3R, 3G, and 3B in this example, the horizontal driving circuit 4 drives the red pixels 3R, the green pixels 3G, and the blue pixels 3B sequentially in a line unit. Thus, as shown in FIG. 10B, the controller 7 outputs the image data D1 so as to repeat the red image data DR, the green image data DG, and the blue image data DB sequentially and cyclically in a line unit.
A timing generator (TG) 11 in the controller 7 generates various timing signals synchronous with the image data D1, and outputs the timing signals to the horizontal driving circuit 4 and the vertical driving circuit 5. Incidentally, the timing signals in this case include, for example, a clock CK (FIG. 10A) of the image data D1, start pulses ST (FIG. 10C) indicating timing of starts and ends of the image data DR, DG, and DB for the respective colors in the image data D1, and strobe pulses (FIG. 10D).
Also, the controller 7 generates original reference voltages VRT, VB to VG, and VRB as a reference for generating reference voltages used for digital-to-analog conversion processing by an original reference voltage generating circuit 12, and then it outputs the original reference voltages VRT, VB to VG, and VRB to the horizontal driving circuit 4.
The horizontal driving circuit 4 inputs the image data D1 output from the controller 7 into a shift register 13, and then it sequentially distributes and outputs the image data D1 to signal line systems of the display unit 2. A reference voltage generating circuit 14 generates reference voltages V1 to V64 as voltages corresponding to gradation levels of the image data D1 from the original reference voltages VRT, VB to VG, and VRB input from the controller 7, and then it outputs the reference voltages V1 to V64.
Digital-to-analog converter circuits (D/A) 15A to 15N each subject output data from the shift register 13 to digital-to-analog conversion processing. Thus, in this example, the digital-to-analog converter circuits 15A to 15N output a driving signal formed by time-division-multiplexing driving signals for three signal lines SIG adjacent to each other. The digital-to-analog converter circuits 15A to 15N perform the digital-to-analog conversion processing on the image data output from the shift register 13 by selecting and outputting the reference voltages V1 to V64 generated by the reference voltage generating circuit 14 according to the output data from the shift register 13.
Amplifier circuits 16A to 16N amplify output signals from the digital-to-analog converter circuits 15A to 15N, respectively, and then output the output signals to the display unit 2. Selectors 17A to 17N in the display unit 2 sequentially and cyclically output the output signals of the amplifier circuits 16A to 16N, respectively, to signal lines SIG for red, green, and blue pixels 3R, 3G, and 3B.
Thus, the driving signal for each signal line SIG is generated by selecting the reference voltages V1 to V64 generated from the original reference voltages VRT, VB to VG, and VRB. FIG. 11 is a block diagram showing a configuration of the original reference voltage generating circuit 12 used to generate the original reference voltages VRT, VB to VG, and VRB and the reference voltage generating circuit 14 used to generate the reference voltages V1 to V64.
The original reference voltage generating circuit 12 has a voltage divider circuit 21 formed by connecting a predetermined number of resistances in series with each other. The voltage divider circuit 21 divides a reference voltage generating voltage VCOM to thereby generate the original reference voltages VRT, VB to VG, and VRB. The original reference voltage generating circuit 12 thus generates the original reference voltages VRT, VB to VG, and VRB by resistance voltage division, and then outputs the original reference voltages VRT, VB to VG, and VRB via amplifier circuits 24A to 24H, respectively. Incidentally, the original reference voltage generating circuit 12 is configured to be able to change voltage applied to the voltage divider circuit 21 by means of a selecting circuit 22 and an inverting amplifier circuit 23 to thereby deal with line reversal or frame reversal. FIG. 10F shows the potential of signal lines SIG in the case of line reversal.
On the other hand, the reference voltage generating circuit 14 has a resistance series circuit 26 formed by connecting voltage divider circuits R1 to R7 in series with each other, the voltage divider circuits R1 to R7 each being formed by connecting a predetermined number of resistances having an equal resistance value in series with each other. The original reference voltages VRT, VB to VG, and VRB are input to one end of the resistance series circuit 26, points of connection between the voltage divider circuits R1 to R7 constituting the resistance series circuit 26, and another end of the resistance series circuit 26 via amplifier circuits 27A to 27H, respectively. Hence, the reference voltage generating circuit 14 further divides potential differences of the original reference voltages VRT, VB to VG, and VRB generated by the original reference voltage generating circuit 12 by the voltage divider circuits R1 to R7, respectively, and thereby generates reference voltages V1 to V64 in a range between the original reference voltages VRT and VRB.
Thus, the numbers of resistances constituting the voltage divider circuits R1 to R7 in the reference voltage generating circuit 14 are each set to a predetermined number so as to generate the reference voltages V1 to V64 from the original reference voltages VRT, VB to VG, and VRB. Thereby, the reference voltage generating circuit 14 can output the plurality of reference voltages V1 to V64 corresponding to gradation levels of the image data D1 by dividing the original reference voltages VRT, VB to VG, and VRB.
In the original reference voltage generating circuit 12, values of the resistances constituting the voltage divider circuit 21 are set so as to display an image with a desired gamma characteristic by using the reference voltages V1 to V64 thus corresponding to the gradation levels of the image data D1. Thereby, as indicated by a reference L1 in FIG. 12, in an example in which the voltage VCOM is set at 5 [V], a desired gamma characteristic is secured by line graph approximation by setting the original reference voltages VRT, VB to VG, and VRB. In addition, the original reference voltage generating circuit 12 allows the original reference voltages VRT, VB to VG, and VRB output from the voltage divider circuit 21 to be changed by altering a wiring pattern. Thus, as indicated by a reference L2 for comparison with the characteristic indicated by the reference L1, in a state in which the original reference voltages VRT and VRB as potentials at both ends are fixed, for example, the gamma characteristic can be varied variously by changing the other original reference voltages VB to VG in ranges indicated by arrows.
Thus, the gamma characteristic can be changed by the setting of the original reference voltage generating circuit 12 for generating the original reference voltages VRT, VB to VG, and VRB. In the liquid crystal display device 1, the controller 7 including the original reference voltage generating circuit 12 is formed by a control IC, while the horizontal driving circuit 4 is formed by a driver IC. Thus, conventionally, a product with a different gamma characteristic can be produced by replacing only the control IC of the liquid crystal display device 1, and thereby in correcting the gamma characteristic, the period of time required for the correction can be shortened. Incidentally, references CA to CH denote stray capacitances between these ICs.
Such flat display devices include a display device formed by organic EL elements. A method has been proposed which sets a gradation level of each organic EL element by driving a signal line SIG in a display unit of such a display device formed by organic EL elements as in the display unit of the liquid crystal display device. Thus, as to the display unit of organic EL elements in such a method, it is conceivable that the control IC and the like in the liquid crystal display device can be used to form the display device.
However, since light emission characteristics of the organic EL elements differ for each color and each product, and the light emission characteristics change with the passage of time, the settings of reference voltages V1 to V64 need to be varied to deal with the difference and change of the light emission characteristics. Therefore, in practice, the display device cannot be formed with the driving circuit of the liquid crystal display device described above with reference to FIG. 8. Specifically, the organic EL elements require black level adjustment and dynamic range adjustment for each color and each product. Incidentally, it is known that the organic EL elements do not require adjustment of a gamma characteristic itself. Therefore, when the original reference voltage generating circuit 12 shown in FIG. 11 is applied, voltages at both ends of the voltage divider circuit 21 need to be adjusted for each color and each product.
One conceivable method for solving this problem is to form an original reference voltage generating circuit as shown in FIG. 13, for example. Specifically, in the original reference voltage generating circuit 30, digital-to-analog converter circuits (D/A) 31A to 31H respectively generate original reference voltages VRT, VB to VG, and VRB according to original reference voltage setting data DV. In this case, the digital-to-analog converter circuits 31A to 31H are formed in the same manner. The digital-to-analog converter circuits 31A to 31H generate a plurality of candidate voltages for the original reference voltages by dividing a reference voltage generating voltage VCOM by a voltage divider circuit 32. A selector 33 selects and outputs the plurality of candidate voltages output from the voltage divider circuit 32 according to the original reference voltage setting data DV.
It is thus possible to set the original reference voltage setting data DV for each color and thereby deal with light emission characteristics different for each color. It is also possible to set the original reference voltage setting data DV for each product and thereby correct variations in the light emission characteristics of the product. In addition, it is possible to deal with change in the light emission characteristics with the passage of time.
With the configuration shown in FIG. 13, however, as shown in FIG. 14, each of the original reference voltages VRT, VB to VG, and VRB can be varied in a range of 0 to VCOM [V]. Hence, when the original reference voltage setting data DV is set erroneously due to noise, the original reference voltages VRT, VB to VG, and VRB are changed in an extreme manner as shown in FIG. 15, for example, thereby degrading image quality significantly.
In addition, in correcting light emission characteristics of such organic EL elements, the organic EL elements with high luminous efficiency require the original reference voltages VB to VG, and VRB to be set so as to suppress a dynamic range of driving signals with respect to the original reference voltage VRT as shown in FIG. 16, in contrast to FIG. 14. In such a case, the configuration shown in FIG. 13 requires resetting of the original reference voltage setting data DV by recalculating the original reference voltages VB to VG of the digital-to-analog converter circuits 31B to 31G so as to correspond to a change in the original reference voltage VRB corresponding to the white level obtained by the lowest voltage. On the other hand, organic EL elements with poor luminous efficiency require the dynamic range to be set so as to be extended. Also, in this case, it is necessary to reset the original reference voltage setting data DV by recalculating the original reference voltages VB to VG so as to correspond to a change in the original reference voltage VRB. Thus, the calculation of the original reference voltages VB to VG is complicated in the adjustment operation at the time of shipment from a factory, for example. Incidentally, black level adjustment also requires the original reference voltages VB to VG of the digital-to-analog converter circuits 31B to 31G to be recalculated so as to correspond to a change in the highest original reference voltage VRT, thus making these calculation operations considerably complicated.